In standard silicon complementary metal oxide semiconductor (CMOS) technology, p-type field effect transistors (pFET) use a boron (or other acceptor) doped p-type polysilicon layer as a gate electrode that is deposited on top of a silicon dioxide or silicon oxynitride gate dielectric layer. The gate voltage is applied through this polysilicon layer to create an inversion channel in the n-type silicon underneath the gate dielectric layer.
For a pFET to work properly, the inversion should begin occurring at slightly negative voltages applied to the polysilicon (poly-Si) gate electrode. This occurs as a consequence of the band alignment for the gate stack structure as depicted in FIG. 1. Specifically, FIG. 1 shows the approximate band alignment across a poly-Si/gate oxide gate stack in a typical pFET at zero gate bias. In FIG. 1, Ec, Ev and Ef are the conduction band edge, valence band edge and the Fermi level in the silicon, respectively. The poly-Si/gate oxide/n-type silicon stack forms a capacitor that swings into inversion at around 0 V and into accumulation around +1 V (depending on the substrate doping). The threshold voltage Vt, which can be interpreted as the voltage at which the inversion starts occurring, is therefore approximately 0 V and the flatband voltage, which is the voltage just beyond which the capacitor starts to swing into accumulation, is approximately +1 V. The exact values of the threshold and flatband voltages have a dependence on the doping level in the silicon substrate, and can be varied somewhat by choosing an appropriate substrate doping level.
In future technology, silicon dioxide or silicon oxynitride dielectrics will be replaced with a gate material that has a higher dielectric constant. These materials are known as “high k” materials with the term “high k” denoting an insulating material whose dielectric constant is greater than 4.0, preferably greater than about 7.0. The dielectric constants mentioned herein are relative to a vacuum unless otherwise specified. Of the various possibilities, hafnium oxide, hafnium silicate, or hafnium silicon oxynitride may be the most suitable replacement candidates for conventional gate dielectrics due to their excellent thermal stability at high temperatures.
Unfortunately, when p-type field effect transistors are fabricated using a dielectric such as hafnium oxide or hafnium silicate, it is a well known problem that the flatband voltage of the device is shifted from its ideal position of close to about +1 V, to about 0+/−300 mV. This shift in flatband voltage is published in C. Hobbs et al., entitled “Fermi Level Pinning at the Poly-Si/Metal Oxide Interface”, 2003 Symposium on VLSI Technology Digest of Technical Papers. Consequently, the threshold voltage of the device is shifted to approximately −1 V. This threshold voltage shift is believed to be a consequence of an intimate interaction between the Hf-based gate oxide layer and the polysilicon layer. One model (See, for example, C. Hobbs, et al., ibid.) speculates that such an interaction causes an increase in the density of states in the silicon band gap at the polysilicon-gate oxide interface, leading to “Fermi level pinning”. Alternatively, oxygen vacancies in the high k dielectric may cause fixed charge, moving the threshold voltage. The threshold voltage therefore is not in the “right” place, i.e., it is too high for a useable CMOS (complementary metal oxide semiconductor) technology.
One possible solution to the above problem of threshold voltage shifting is by substrate engineering in which channel implants can be used to shift thresholds. Although substrate engineering is one possible means to stabilize threshold voltage shift, it can do so to a limited extent, which is inadequate for FETs, particularly pFETs, that include a gate stack comprising a poly-Si gate electrode and a hafium-containing high dielectric constant gate dielectric.
Another possible solution to the problem of threshold voltage shifting mentioned above is by providing an insulating interlayer between the conductive material and dielectric material such as is described, for example, in co-pending and co-assigned in U.S. Ser. No. 10/845,719, filed May 14, 2004, U.S. Ser. No. 10/863,830, filed Jun. 4, 2004, and U.S. Ser. No. 11/035,889, filed Jan. 14, 2005. The entire contents of each of the aforementioned U.S. Patent applications are incorporated herein by reference in their entirety.
A yet other possible solution to the above problem of threshold voltage shifting is to increase the Si content of the dielectric material. This solution has been described by E. Cartier, et al., entitled “Systematic study of pFET Vt with Hf-based stacks with poly-Si and FUSI gates”, 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004 IEEE, pp. 44-45; C. Hobbs, et al., entitled “Factors Influencing the Threshold Voltages of Metal Oxide CMOS Devices”, ECS2004; W. Deweerd, et al., entitled “Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey”, Microelectronics Reliability 25, (2205), pp. 786-789; C. Hobbs, et al., entitled “Fermi Level Pinning at the PolySi/Metal oxide Interface”, 2003 Symposium on VLSI Technology Digest of Technical Papers, 2003 IEEE; and C. Hobbs, et al., entitled “Fermi-Level Pinning at the Polysilicon/Metal Oxide Interface—Part I”, IEEE Transactions on Electron Devices, Vol. 51, No. 6, June 2004, pp. 971-977.
Although the various techniques alone have been used to improve the problem of threshold voltage shifting, further improvement is still needed. For example, the use of an insulating interlayer such as Al(O)N deposited onto a HfO2 and a low Si content HfSiO (Si content of lower than 50%) dielectric has provided Vt improvement by up to 0.35 V. Additional measures are needed that can bridge the remaining cap to provide a total of 0.6 V; the total magnitude Vt observed for gate stack including polySi and HfO2 or a low Si content HfSiO. Similar measures are also needed when high Si content dielectrics are used alone. Implant channel engineering can also move the threshold voltage, but may cause performance degradation and/or enhanced short channel effects.
To date, the prior art utilizes only a single means to reduce the threshold voltage shift described above. The applicants of the present invention have determined that by combining a high k dielectric with a high Si or Ge content with an insulating interlayer and/or by channel engineering, the shift in threshold and flatband voltages are almost eliminated.